Logic, Memory & Foundry
Advanced-node economics (3nm/2nm), DRAM and NAND cycles, TSMC-Samsung-Intel dynamics.
MeridianConsensus
Decision-grade Market IntelligenceAny market · any geography
Semiconductor geopolitics is now first-order. We cover logic, memory, analog, SoC, compound semis (SiC, GaN), equipment (EUV, deposition, etch), and the electronics value chain from foundry to OEM.
Semiconductor geopolitics is now first-order. We cover logic, memory, analog, SoC, compound semis (SiC, GaN), equipment (EUV, deposition, etch), and the electronics value chain from foundry to OEM.
Every sub-sector below is commissionable as a standalone 30-chapter study, or scoped bespoke for investment-committee and diligence use.
Advanced-node economics (3nm/2nm), DRAM and NAND cycles, TSMC-Samsung-Intel dynamics.
Analog ICs, power management, SiC/GaN adoption in EV and industrial applications.
EUV, deposition, etch, test, metrology, capex cycles and geopolitical restrictions.
Passive components, PCB, connectors, displays, OEM supply-chain and price-cost pass-through.
CMOS image sensors, automotive MEMS, industrial sensors, and IoT-edge hardware.
Auto MCUs, SiC inverter chips, ADAS SoCs, and supplier-OEM dynamics.
Every commissioned semiconductors & electronics study ships as an interactive dashboard, size and trajectory, ranked share, regional cuts, segmentation. Hover every bar to see the underlying figure; every number is traceable to a named source.
The priorities our research committee is tracking across the sector this quarter. Sub-sectors describe structure; themes describe motion. Reports commissioned against these themes ship with the latest signal-read baked in.
Node-threshold, equipment-class, and entity-list expansions; allied-block coordination.
Arizona fab timelines, yield economics, and advanced-packaging capacity siting.
HBM3E/HBM4 capacity constraints; DRAM-maker capex-ROI; merchant-GPU share dynamics.
OEM SiC-inverter adoption, 800V architecture migration, and SiC-substrate supply economics.
Allied-export-control alignment; second-tier equipment-supplier market-share gains.
TSMC CoWoS, Samsung SAINT-D, Intel Foveros, packaging capex outpacing front-end; OSAT (ASE, Amkor, SPIL) capacity economics and substrate-supplier bottleneck.
Post-2022 over-ordering digesting through 2025 in mature-node auto MCUs; 2026 margin-recovery thesis for NXP / Infineon / STMicro / Renesas.
UCIe-ratified chiplet interconnect unlocking mix-and-match die sourcing; EDA-tool and advanced-packaging revenue pool implications.
The four teams that most commonly commission semiconductors & electronics research. Each role below maps to a specific use-case the commissioned study is scoped against, from diligence to annual planning.
Logic, analog, and equipment acquisition diligence with supply-chain and export-control context.
Supply-chain mapping, capacity-siting analysis, and advanced-packaging capability assessment.
Chiplet, EDA, compound-semi, and AI-hardware thesis validation.
Cycle-position, TAM re-estimation, and AI-training capex context for semi and equipment coverage.
Same methodology, same committee review, same written support. If you can describe the sub-sector, we can commission the study, accessible instantly on demand. Any geography, any boundary.
Intel Watchlist · from $89/mo
Senior Analyst Support ships an always-on intel feed: M&A 8-Ks, exec moves, regulatory dockets, and patent filings on semiconductors & electronics. Email + Slack delivery. Cancel any time.